1. Field of the Invention
The present invention relates to message bus architectures used in digital systems, and more specifically to a method and apparatus for reducing the number of additional signal lines to be provided for control signals in a message bus.
2. Related Art
A parallel message bus (hereafter “message bus”) generally contains a number of signal lines, which can transfer signals in parallel. In a typical scenario, multiple modules are connected to a message bus, and each module can send data (in the form of signals) to the other modules using the message bus. An arbitrator generally grants ownership of the message bus to only one of the modules, which can then send data to one or more of the other modules using the signal lines in the message bus.
Signal lines (contained in the message bus) generally need to support various control/status paths (in addition to data paths) to supervise the flow of data between various modules connected to the message bus. The control/status signals, for example, may represent signals such as bus request, bus grant (allocation) and signals which depict current status of the modules and status of the data transfer.
A parallel message bus is often designed to meet several requirements such as reduction in the width of the bus, support for higher bandwidth, etc. Reducing the width of the bus leads to corresponding reduction in number of interconnections (resulting in reduced cost of the system), reduction in power consumption as well as reduced area requirements.
In one prior embodiment referred to as a Peripheral Component Interconnect (PCI) bus supporting 64-bit data transfer, the bus is defined with 64 signal lines to transfer 64 data bits in parallel, and a number of additional signal lines dedicated for control purposes (and the number of such paths supporting control/status signals is high). It maybe desirable to reduce such number of additional signal lines required for sending control signals (or, the bus width, in general) further.